The 2nd Edition of Contemporary Logic Design is renowned for its transition from discrete logic to modern programmable logic devices (PLDs) and Field Programmable Gate Arrays (FPGAs). Consequently, the solution manual mirrors this structure, offering guidance across several key domains:
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A 1K × 8 SRAM has a read cycle time of 20 ns and a write cycle time of 25 ns. What is the maximum read rate in MB/s? How many address lines does it have?